1. Field of the Invention
This invention relates generally to low power digital logic devices, and more particularly to a technique for achieving very low Ioff and Ioz leakage in low power digital logic devices that incorporate Ioff and overvoltage tolerance.
2. Description of the Prior Art
Known Ioff/overvoltage blocking circuits use a PN diode in parallel with a Schottky diode and can not achieve very low leakage levels for both Ioff and Ioz. The inherent reverse leakage of a Schottky diode causes Ioff to be undesirably high for certain low power applications. A PN diode alone will not provide enough forward leakage to keep the upper output driver (UOP) fully turned off during Ioz conditions—resulting in Ioz values that are undesirably high.
In view of the foregoing, it would be both beneficial and advantageous to provide a technique for achieving very low Ioff and Ioz leakage in low power digital logic devices that incorporate Ioff and overvoltage tolerance.